The present invention relates to the field of electronic design automation (EDA) or computer aided design (CAD) software and, more particularly, to techniques for placing devices and routing interconnects, especially clock signal lines, in integrated circuits.
Integrated circuit technology is a marvel of the modem age. Integrated circuits are also sometimes referred to as “chips.” Integrated circuits are used in many applications such as computers, consumer electronics, networking, and telecommunications. There are many types of integrated circuits including microprocessors, microcontrollers, application specific integrated circuits (ASICs), gate arrays, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and Flash memories. Integrated circuits may also include combinations of one or more of these specific types of integrated circuit. For example, an ASIC may include a portion of an embedded DRAM.
Integrated circuit technology continues to rapidly advance. Modern integrated circuits may contain hundreds, thousands, or even millions of individual devices (e.g., transistors, resistors, diodes, capacitors, and others) or cells. Such designs are much too large for an integrated circuit designer to manage effectively manually. For example, an integrated circuit design may have hundreds or thousands of inputs and outputs that need to be routed. To route interconnect manually between the inputs and outputs, it would take an integrated circuit designer an inordinate amount of time.
Therefore, automation tools are needed to make easier and expedite the task of designing an integrated circuit. It is important to be able to produce a circuit design and layout meeting or exceeding the design objectives before the integrated circuit is fabricated. This will help avoid a costly redesign to correct errors or improve performance to meet specifications. Techniques are needed to provide high-performance circuit designs and circuit layouts.
Speed in the design process is also an important consideration for an EDA system. Time-to-market pressures demand design tools provide rapid, accurate results, especially for large complex designs. By obtaining results more quickly, designers can make more meaningful decisions on design tradeoffs by not having to wait for days to even weeks to obtain accurate results.
As a component of an EDA system, automatic interconnect routers, or routers, have been developed to automate the placement of interconnects in integrated circuit devices. Routers generate the geometry of the interconnects to connect pins or a network of pins together. Traditional routers typically include a coarse routing process and a fine routing process. The coarse router provides a general path for interconnect routing. The fine router provides the actual interconnect segments and their geometries. The fine router creates interconnect routes that are “clean.” Clean refers to making routes that do not have design rule violations (such as meeting timing, crosstalk, and antenna effect specifications) and do not overlap other structures (such as other interconnect routes and obstacles).
It is desirable to provide better or improved routing quality when using an automatic router. Better routing quality refers to an improved routing pattern or design in order to enhance signal propagation characteristics, such as reducing noise, reducing signal propagation time, and other signal characteristics. In particular, traditional routers do not necessarily generate optimal linear interconnects. For example, a traditional router often produces interconnect with many jogs and bends, which do not facilitate a fast signal path. Linear interconnects are desirable so as to improve integrated circuit performance, reduce resistance and capacitance of interconnects, reduce die size, and improve circuit layout organization.
As a result of the shortcomings of traditional automatic routers, integrated circuit designers manually reroute interconnects to increase linear interconnects. However, manual rerouting is time consuming, especially for large designs, may introduce design rule violations, and the results of manual rerouting may not be optimal.
As can be seen, techniques are needed to route interconnects, especially clock signal lines, of integrated circuits in an optimal way for improving designs, especially improving the routing quality and speed of automated routing.